%FILENAME%
vtr-9.0.0-1.2-x86_64_v3.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1.2

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
9068465

%ISIZE%
29742084

%SHA256SUM%
6ae5d8138071a124704695b1633be1d2f273c55306cbee496b476ae364d2a998

%PGPSIG%
iQGzBAABCgAdFiEEiC3P5I4gUdSOJWKr87YHSI2zWkcFAmhPZ+wACgkQ87YHSI2zWkciggv/a+l8p60nsuKvbv6kZv4pBH1xyAnow8U+MAX7AArXvogI9AUcrZo9V/c1uK6rCgcSfCr6/7CTj/G7SiZixNgqOg7XlHLKv1zPRfR9hlzjPdWID4SKYuGQqYtaU/jiWbJUu3plghlbr+JWYbLXMlFkndZ+gwWBZvwW1mDv8nvvV4MNUllXR40Pt+p86W84UwQ07AYb04n2aRW796LlpGONSlMhjtj8LxxZQSK+WWdpTDpNWbxDsccoR0VJbEhuup+s6krsjo8ZFisCIm+WecPEVKSFnP8Jm5aJAwjBKbO8734GdNXs1LcgB/tZ9BYmoRwUBLqYq2pUAEyIklHWNYMiwW9HZFmunDmGsntZicALQI5NvXrzQQZTUjyTrPcbiIwSKnzgCrB0wx+JyZsH5AQyTXgckHd5mZV1oPfJRArQkmbPiia74K+yp1XmFl+UffKClOpQ92lurKgi1G5dBT6H7WygCfI+tY8d6AQJqWhDGkNrJs+LPBxiv4/myyUQkCNO

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64_v3

%BUILDDATE%
1750034195

%PACKAGER%
CachyOS <admin@cachyos.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

